Advancements in micromachining and other microfabrication techniques and processes have enabled the fabrication of a wide variety of MicroElectroMechanical Systems (MEMS) and devices. These include moving rotors, gears, switches, accelerometers, miniaturized sensors, actuator systems, and other such structures.
One popular approach for forming MEMS devices makes use of a modified wafer known as a Silicon-On-Insulator (SOI) wafer. An SOI wafer is essentially a silicon handle wafer having a silicon dioxide sacrificial layer disposed thereon, and having a device layer of active single-crystalline silicon disposed on the sacrificial layer. FIGS. 1-3 illustrate a conventional method for creating a MEMS structure on an SOI wafer. As shown in FIG. 1, in accordance with this method, a silicon wafer substrate 15 is provided having a silicon dioxide sacrificial layer 13 disposed thereon. A layer of active single crystal silicon 11 is disposed over the sacrificial layer. The layer of active single-crystal silicon is then masked, patterned and selectively etched to yield the structure shown in FIG. 2, after which the sacrificial layer is partially removed by selective chemical etching to release the structure. As shown in FIG. 3, the released MEMS structure 12 has a cantilevered portion 17 formed of Si and an anchor portion 19 formed of SiO2.
The methodology depicted in FIGS. 1-3 suffers from a number of drawbacks, one being its reliance on partial chemical etching to define the anchor structure perimeter. Chemical etch rates can vary considerably from one product lot to another in an SOI fabrication scheme, due, for example, to variations in temperature, in the pH of the etching solution, and in the composition of the dielectric material being etched. In a fabrication scheme which relies on partial chemical etching, these variations in etch rates result in variations in the size of the anchor perimeter of the device. Consequently, in order to account for these variations and to ensure that a perimeter having a desired minimum circumference is achieved, SOI devices are typically designed with anchor perimeters that are significantly larger than would be necessary if etching were more predictable. However, the use of a perimeter that is larger than necessary is undesirable in that it increases the overall die area, and also leads to larger parasitic capacitance between the anchor and the substrate.
One solution to this problem has been proposed in commonly assigned U.S. patent application Ser. No. 10/238,062 (O'Brien et al.) filed on Sep. 9, 2002. That reference describes a method for creating a MEMS structure in which a first trench is created in the SOI structure which extends through the silicon layer and the sacrificial layer and which separates the sacrificial layer into a first region enclosed by the first trench and a second region exterior to the first trench. A first material is deposited into the first trench such that the first material fills the first trench to a depth at least equal to the thickness of the sacrificial layer. A second trench is created exterior to the first trench which extends through at least the silicon layer and exposes at least a portion of the second region of the sacrificial layer. The second region of the sacrificial layer is then contacted, by way of the second trench, with a chemical etching solution which is adapted to etch the sacrificial layer and which is selective to the first material. Since the material disposed in the first trench acts as a barrier to the etch, the timing of the etch is no longer critical, and MEMS structures may be produced through this approach which have anchor portions that do not vary significantly from one batch to another. Consequently, the anchor perimeter can be minimized, thereby minimizing parasitic capacitance and resulting in a reduction in die size.
While the methodology of O'Brien et al. is a notable advancement in the art, its use nonetheless has some disadvantages in certain applications. In particular, the approach of O'Brien et al. relies on deep reactive ion etching (RIE) of both the device silicon and the sacrificial layer to form the anchor portion of the device. However, the etch rate of the sacrificial layer at the bottom of a deep and narrow trench extending all the way through the device layer is rather slow. While a wet etch could be used to etch the portion of the sacrificial layer at the bottom of the trench, the undercut typically caused by such an etch would result in undesirable void formation in the anchor area during backfill of the trench. The approach of O'Brien et al. also results in a device in which the anchor material is a different material than the single crystal silicon used in the device layer, which makes it more difficult to integrate with CMOS devices and other such structures.
There is thus a need in the art for a method for producing a MEMS structure on a substrate, and particularly from an SOI wafer, such that the perimeter of the anchor portion of the structure (and hence the wafer size) can be minimized, is not affected by variations in etch rates, and does not vary significantly from one product batch to another. There is also a need in the art for a method for producing a MEMS structure, and particularly for forming an anchor portion thereof, that does not require reactive ion etching of the sacrificial layer at the bottom of a trench extending through the device layer thickness. These and other needs are met by the methodologies and devices disclosed herein and hereinafter described.